1. Field of the Invention
The present invention relates to the field of power management. More particularly, the present invention relates to a circuit and method for preventing corruption of CMOS memory during a power-down sequence.
2. Description of Art Related to the Invention
For many years, power supplies have been installed into a majority of personal computers ("PCs") in order to convert power from a wall socket into a power level used by one or more printed circuit boards implemented within the PC. For less advanced power supplies, the supply of power has been controlled by hardware-initiated, power-down sequences commenced by manually depressing a button or switch protruding from the casing of the PC. When turned on, the power supply provides a steady direct current ("DC") voltage to the printed circuit board. This DC voltage, referred to as "V.sub.cc ", is usually 5 volts. When turned off, however, the power supply switches to provide a standby voltage ("V.sub.(stby) ") with a minimal amount of current (e.g., typically 10 milliamperes "ma"), which provides sufficient power to support various electrical components requiring power at all times.
Independent of the type of power supply implemented within the PC, a battery may be added to the printed circuit board to provide a backup voltage (referred to as "V.sub.bat "). This battery may be necessary in order to provide power to the electrical components in the event that the power supply is disconnected from the wall socket. Examples of such electrical components include a real time clock and battery-backed CMOS random access memory as discussed below.
Typically, a volatile memory element is implemented within the PC in order to store system configuration information. This volatile memory element is usually memory fabricated through a Complementary Metal-Oxide Semiconductor ("CMOS") process (hereinafter referred to as "CMOS memory"). Typically, CMOS memory requires very low power and is contained in a Super Input/Output ("SIO") component. CMOS memory must always remain powered to avoid loss of its stored content which are always checked during power-up. Therefore, CMOS memory switches between V.sub.bat, V.sub.(stby) and V.sub.cc depending on the current state of the power supply.
Unlike less advanced power supplies, emerging power supplies are being designed with the ability of receiving a control signal from one of the printed circuit boards in the PC, such as the motherboard, to turn on or off the power supply. Examples of the emerging power supplies include, but are not limited to ATX and LPX power supplies which have different connectors. These power supplies enable the PC to support advanced power management software, advanced power supply control software and other widely available power management software which, initiates a software-controlled, power-down sequence.
Currently, during a power-down sequence by the PC, the SIO component is configured to prevent access to its CMOS memory after receipt of an active system RESET signal derived from the power supply. This access prevention technique can be enhanced significantly in those cases where CMOS memory may be accessed after the printed circuit board has initiated a power-down sequence, but before the active system RESET signal has been received by the SIO component. CMOS memory corruption is likely to occur during the power-down sequence. CMOS memory corruption is most troublesome at motherboard manufacture when numerous power-down and power-up sequences are being performed.
The disadvantages of CMOS corruption are self-evident in increased manufacturing costs to temporarily correct printed circuit boards found to be defective. For those printed circuit boards that are not found to be defective, there is a possibility that PC users may occasionally experience CMOS corruption requiring reconfiguration for his or her PC. These problems can increase the cost of a product unnecessarily.
Thus, it would be advantageous to provide a circuit and technique that prevents access to the CMOS memory as early as possible in the power-down sequence to prevent CMOS memory corruption.